Tran Phong
I am a robotics software engineer at Dyson, Singapore, working in mapping and motion planning for vaccum robot. I was with Fujitsu-SMU Urban Computing and Engineering (UNiCEN) Corp. Lab, under supervision of Professor Lau Hoong Chuin, where I worked in joint projects funded by Y3 and uParcel to engineer routing engines for logistics companies. I obtained Master in Computer Sceicne from NUS, School of Computing. I worked with Professor David Hsu for motion prediction and planning benchmarking project for autonomous driving car in my dissertation.
Email / Google Scholar / Github
Research
During undergraduates, I had one year as a visiting student at NTU, Singapore where I worked with Professor Siew Kei Lam and Dr. Thinh Pham on a hardware acceleration project for ORB object detection in self-driving cars system. During the time at NUS, I studied the effects of different motion prediction models on the performance of motion planning algorithms.
I am interested in autonomous driving, especially in motion prediction and planning. My current research focuses on planning under uncertainty by formulating the problem as a POMDP. I am fascinated to explore how we can have an interpretable, safe, and robust planning for self-driving car. Towards that ends, I posit the consideration of three guiding design concepts: (i) robust vision to detect objects (e.g., occupancy network, scene flow estimation), (ii) jointly trained all modules in stack to reduce error propagation and (iii) language models to intelligently plan and explain the decision.
Publications
Advances in Neural Information Processing Systems 36 (NeurIPS 2023)
Proceedings of the International Conference on Automated Planning and Scheduling (ICAPS), China, 2021
IEEE International Conference on Field-Programmable Technology (ICFPT), Japan, 2018
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 747 - 756, December 2018
Work Experience
Routing Engine for Y3 Technologies
Fujitsu-SMU Corp Lab, March 2021 - now
In this work, I extend our developed engine to cater for three main requirements from Y3 Technoligies: compatibility constraints (relationship between vehicles and locations), dynamic time/distance matrix (due to road construction) and optimized costs for each delivery routes.
Fujitsu-SMU Corp Lab, March 2019 - March 2021
I developed two neural network models: i) WCGAN combined with linear regression on tabular inputs and ii) Spatial-Temporal network in addition with VAE on images data to predict the crimes' locations and occurences. I also implemented local search to plan ahead of the patrol shift work plans with minimum time shift between locations.
Collaborative Urban Delivery Optimization
Fujitsu-SMU Corp Lab, March 2019 - March 2021
In this work, I used machine learning to predict the estimated time of arrival (ETA) between two locations. I proposed a time-slot division strategy to find the lowest number of vehicles before the neighborhood search and post-optimized the schedule plans with redistributions of orders while violating minimum of soft constraints. I also engineered the frontend and backend of the system.
Projects
Sashankh Chengavalli Kumar, Tran Phong, Wong Wei Hao
In this project, we aim to study deep learning approaches to a text classification task, by attempting to predict the genre of a film based on its plot in a single-label multi-class classification problem.
Apivich Hemachandra, Tran Phong
We designed cache-efficient (cache-oblivious and cache-adaptive) algorithms for matrix multiplication and experimented on a simulated cache and a real computer.
Lim Sze Chi, Tran Phong
We developed Deep Q-Learning to automate the Duckiebot to follow the lane and reduce speed near the traffic light. We also employed Autoencoder network to extract good features.
Le Minh Quang, Tran Phong
We collected comprehensive data of all Vietnamese characters to support the thesis proposal and applied a standard CNN model to recognize Vietnamese characters with 95% top-1 accuracy.
Tran Phong
We designed a core CPU (LC3b) architecture of Illinois University with Verilog language, verified by VCS tool in Linux environment, and evaluated on FPGA (DEII Kit of Altera company). We proposed a pipeline architecture that functioned properly sixteen machine instructions and achieved 125 Mhz.
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